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Digital System Design (ELX404)
Unit 1 Sequential logic design
Session 1 : Mealy and Moore models, state machine notations
Session 2 : clocked synchronous state machine analysis
Session 3 : construction of state diagram, sequence detector (word problem),
Session 4 : state reduction techniques (inspection, partition and implication chart method)
Session 5 : clocked synchronous state machine design
Session 6 : design examples like a few simple machines and traffic light controller, vending machine
Unit 2 Algorithmic State Machine (ASM) Chart and Register Transfer Luanguage(RTL)
Session 7 : Standard symbols for ASM Chart, Realization techniques for sequential/logic functions using ASM Chart,
Session 8 : Top Down Design Example, Generalized ASM output
Session 9 : ASM Chart representation of control unit, RTL
Session 10 : Construction of data unit using RTL Description, Timing of connection and transfer
Session 11 : sequencing of control, Combinational logic and conditional transfer
Session 12 : Graphical and RTL Bus notation, Design examples of waveform controllable generator
Session 13 : pulse width adjustor using ASM chart
Session 14 : design data unit and control unit for sequential circuits using RTL Description
Unit 3 Sequential logic design practices
Session 15 : Synchronous counter design and applications
Session 16 : MSI asynchronous counters (IC 7490, 7493)
Session 17 : MSI synchronous counters (IC 74161, 74163, 74168, 74169) and applications
Session 18 : decoding binary counter states, MSI shift registers
Session 19 : Synchronous design methodology, impediments in synchronous design
Session 20 : synchronizer failure and metastability
Unit 4 Introduction to VHDL
Session 21 : Introduction to Hardware Description Language
Session 22 : Core features of VHDL, data types
Session 23 : concurrent and sequential statements, data flow
Session 24 : behavioral, structural architectures, subprograms
Session 25 : Examples like Adder, subtractor, Multiplexers
Session 26 : De-multiplexers, encoder, decoder
Unit 5 Design of Sequential circuits using VHDL
Session 27 : VHDL code for flip flop, counters, registers, Moore
Session 28 : Mealy type FSMs, Serial adders, sequence detector
Unit 6 Programmable Logic Devices
Session 29 : ROM, RAM, SRAM, PLA, PAL, CPLD and FPGA architecture
Session 30 : Numerical based on PLA and PAL.
Session 10 : Construction of data unit using RTL Description, Timing of connection and transfer
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